1. Field of the Invention
The invention generally relates to memory devices and more particularly relates to dynamically controlling the transfer of data being read from a memory device.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Herein, such memory devices are collectively referred to as DRAM devices.
Some types of DRAM devices have a synchronous interface, generally meaning that data is written to and read from the devices in conjunction with a clock pulse. Early synchronous DRAM (SDRAM) devices transferred a single bit of data per clock cycle (e.g., on a rising edge) and are appropriately referred to as single data rate (SDR) SDRAM devices. Later developed double-data rate (DDR) SDRAM devices included input/output (I/O) buffers that transfer a bit of data on both rising and falling edges of the clock signal, thereby doubling the effective data transfer rate. Still other types of SDRAM devices, referred to as DDR-II SDRAM devices, transfer two bits of data on each clock edge, typically by operating the I/O buffers at twice the frequency of the clock signal, again doubling the data transfer rate (to 4× the SDR data transfer rate).
Data read out from such DDR devices is often held in first-in first-out (FIFO) structures that receive the data from the memory arrays and drive the data out onto external data lines. Input and output pointers are typically used to determine (or “point to”) a FIFO location to which data is to be input to or output from the FIFO, respectively. These pointers are typically derived from a signal that is essentially generated as a prediction of when the data should be valid at the FIFO, based on predicted delay through components in the data path. The output pointers ensure the synchronous requirements of data output from the DRAM are satisfied.
Transmitting the data from the memory arrays to the FIFO typically involves primary sense amplifiers and a secondary sense amplifier. Specifically, data read out from the memory arrays is driven onto sense lines by the primary sense amplifiers. Secondary sense amplifiers amplify the data from the sense lines and drive the data to the FIFO.
Driving the data from the secondary sense amplifier to the FIFO is done on the basis of a predefined delay in order to ensure the data signal is sufficiently developed. Typically, this predefined delay is set to ensure that the slowest device performance is accommodated, with some additional margin. However, determining this predefined delay is difficult since many factors can affect the performance of a given chip. For example, the manufacturing process itself produces transistors of varying strengths. In operation, the voltage levels and the temperature affect performance. Accordingly, the predefined delay must accommodate these and other factors and variables. At the same time, in order to achieve the fastest performance possible, it is undesirable to set the predefined delay any later than necessary. Accordingly, establishing the secondary sense amplifier delay is a balancing of yield (i.e., the measure of the number of chips that satisfy certain predefined performance criteria) and performance. The greater the yield (attained by setting a relatively more relaxed secondary sense amplifier timing) the lesser the performance, and vice versa.
Because of the difficulty in determining the optimal delay before setting the secondary sense amplifier, and the necessary loss of some performance to accommodate margins, the conventional approach of using a fixed delay is undesirable. Therefore, what is needed is an apparatus and method for dynamically setting the secondary sense amplifiers.